AR# 51756

Description

Solution

• Timing results are incorrect if design is not reloaded as checkpoint.
• Slow elaboration performance due to security conflict in isl_iostreams library on some customer systems
• Synthesis -effort_level quick generates incorrect netlists.
• (Xilinx Answer 51016) - Router is not honoring "DIRT" strings required to create routed designs for Virtex-7 HT.
• (Xilinx Answer 50976) - The 2012.2 Vivado Install is not creating a Vivado entry in the Start menu or program group on Windows 32-bit
• Targeting a Zynq device with Xilinx Platform Studio Pcore export is not enabled in Vivado HLS with Vivado System Edition license
• An enable signal to floating point cores is being transitioned incorrectly when using Vivado HLS
• Router bug causes an invalid bitstream. Routing fails but bitstream generation is successful.
• DRC ERROR missing for Router Critical Warnings for illegally routed design.
• Specific Virtex-7 DRC error is only reported during write_bitfile DRC.
• After running opt_design and writing out another checkpoint, the order of the XDC constraint files in the checkpoint xdc is changed (possibly invalidating constraints due to ordering).

In addition to addressing the above Issues, the Install Definition for the update was fixed to enable program group detection in Updater and to allow Xilinx Notify to alert customers of the update availability.

The update is approximately 500 MB in size and is intended to be installed on top of a Xilinx Design Tools 14.2/2012.2 install.

The update is available at: http://www.xilinx.com/download