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AR# 51808

Vivado - How can I write out a list of the source files (Verilog, VHDL, netlist etc.) from Vivado IDE?

I would like to write out a list of source files that have been added to my Vivado project. How can this be done?

You can use the get_files command in the Tcl console:

% get_files

If you want specific types, then use:

% get_files -filter {FILE_TYPE == Verilog}

If you really want to know what are the source files in your Source Set, then use:

% get_files -of_objects [get_filesets sources_1]

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