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AR# 51813

14.2 BitGen - "ERROR:Bitgen:342 occurs after adding probes to the design in the case of 7 series devices"


An error similar to the following occurs in BitGen after adding the probes to the design in FPGA editor in the case of 7 series devices:

"ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned. This might cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you may apply the following bitgen switch: -g UnconstrainedPins:Allow
This message applies to the following I/O ports"

This error message occurs even after I assign proper locations and I/O standards to all the I/O ports of the design.


For the 7 series family, BitGen issues this error message if there are any I/O ports in the design that are not assigned locations or have an undefined I/O Standard. For more information on the error message, refer to (Xilinx Answer 41615).

This error message is also reported when the BitGen is run after adding the probes to the design in the FPGA editor. It is an incorrect error message, as all the I/O ports in the design are assigned to proper locations and I/O standards.

One way to work around this error is to use the -g UnconstrainedPins:Allow switch in BitGen.

This issue is scheduled to be fixed in FPGA Editor 14.5.

Linked Answer Records

Associated Answer Records

AR# 51813
Date 02/13/2013
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • ISE Design Suite - 14.2
  • ISE Design Suite - 14.3