Description

Vivado Design Suite 2012.3 generates the following error in the Placer phase when the XADC auxiliary inputs are used as analog inputs in a bank:

Phase 7.1.1 IO / Clock Placer
ERROR: [Place 30-372] Bank.15 has locked terminals with incompatible standards: Incompatible Pair of IO Standards: LVCMOS25 and LVCMOS18 The following terminals correspond to these IO Standards:
SioStd: LVCMOS25 VCCO = 2.5 Termination: 0 TermDir: In Bank: 15 Placed : Term: RS232_Uart_1_sin
SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In Bank: 15 Placed : Term: axi_xadc_0_VAUXN_pin

Solution

The auxiliary inputs can be used as either analog or digital inputs. If they are used as analog inputs, they need to adhere to the analog input specification rather than the digital specifications.

• Vivado Design Suite 2012.2 requires all I/Os to have a valid IOSTANDARD specified for 7 Series devices.
• Vivado Design Suite 2013.2 requires all I/Os to have a valid IOSTANDARD specified for Zynq 7000 devices.

If no IOSTANDARD is selected, the tools use the default IOSTANDARD of LVCMOS25; and, if the other digital I/Os in the bank require a VCCO of 3.3V, the two are determined to be incompatible and the error is issued.

If there are no bank compatibility issue, the Placer will not issue the error but write_bitstream will issue an error due to the DEFAULT IOSTANDARD being used for the XADC inputs.

[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 2 out of 250 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value

There is no analog input IOSTANDARD available in the Vivado tool. To work around the Placer and write_bitstream error, you can define any IOSTANDARD that is compatible with the digital I/Os in the bank.

For example, if the digital I/Os are LVCMOS33, you can define the auxiliary inputs as LVCMOS33 as well.

Note: The auxiliary inputs will still be treated as analog inputs based on whether they are connected to the auxiliary inputs of the XADC in the design.

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