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AR# 51871

Virtex-6 FPGA Integrated Block for PCI Express v2.4/v2.5 - Missing MRds following PCIe hot reset

Description

Version Found: v2.5
Version Resolved and other Known Issues: See (Xilinx Answer 45723)

After a PCIe hot reset, the endpoint does not respond to the host's memory read (MRd). 

The MRd does not appear at the AXI RX port.

Solution

In Gen2 x8, the MRd does not appear at the AXI RX port because in trn_rx_128.v, one counter (i.e., u_cnt) is not reset by the hot reset.

Fundamentally, u_cnt and b_cnt are covered by different resets.

To work around this issue, make the following modification in the toplevel <component_name>.v file:

From

  // Generate user_reset_out
FDCP #(
  .INIT(1'b1)
) trn_reset_n_i (
  .Q (user_reset_out),
  .D (!(trn_reset_n_int1 & ~phy_rdy_n)),
  .C (user_clk_out),
  .CLR (~sys_reset_n_d),
  .PRE (1'b0)
);

To

  // Generate user_reset_out
FDCP #(
  .INIT(1'b1)
) trn_reset_n_i
  (v    .Q (user_reset_out),
   .D (!(trn_reset_n_int1 & ~phy_rdy_n & ~pl_received_hot_rst)),
   .C (user_clk_out),
   .CLR (~sys_reset_n_d),
   .PRE (1'b0)
);

Though the issue is found in Gen2 x8, the work-around can be applied to all configurations.

Revision History
09/05/2013 - Initial release

AR# 51871
Date Created 09/18/2012
Last Updated 03/25/2015
Status Active
Type General Article
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )