The PHY providesthe physical interface to an external DDR2 or DDR3 SDRAM. The PHY generates the signal timing and sequencing required to interface to the memory device. It contains the clock-, address-, and control-generation logic, write and read datapaths, and state logic for initializing the SDRAM memory after power-up. In addition, the PHY contains calibration logic to perform timing training of the read and write data paths to account for system static and dynamic delays.
The 7 Series FPGAs Memory Interface Solutions User Guide includes a detailed section on the PHY logic. Please review this material within the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
This section of the MIG 7 Series Design Assistant focuses on the design of the PHY logic and the interface between the PHY and the controller. It is divided into the following categories:
PHY Signal, UCF Constraint,and RTL Parameter Descriptions (Xilinx Answer 51914)