Description

Solution

Parameter Descriptions
The MIG 7 Series DDR3/DDR2 designs is parameterized by numerous top-level parameters and local-rtl parameters. The local-rtl parameters do not change and should never be edited by a user. Based on the GUI selections and pin-out, MIG properly sets the top-level rtlparameters . The DDR2 and DDR3 Memory Interface Solution > Customizing the Core section of the 7 Series FPGAs Memory Interface Solutions User Guide includes tables which detail each of these top-level rtl parameters. These parameters range from setting up signal widths, simulation options, clock settings, memory controller operation, SDRAM configuration, and mapping of the hard blocks based on the pin-out.

Changes to the pin-out after the MIG 7 Series core has been generated should be ran through the Verify UCF and Update Design feature within the MIG 7 Series tool. The top-level rtl parameters such as BYTE_LANES_B*, DATA_CTL_B*, PHY_*_BITLANES, *_MAP (i.e., ADDR_MAP) are specifically set based on the pin-out MIG 7 Series generates. A combination of thesemapping parameter settings and UCF LOC constraints set-up the appropriate routing and usage of the hard blocks.A change to the pin-out invalidates these settings.

UCF Constraints
The UCF not only includes timing constraints and pin LOCs for the generated design but also LOC and configuration constraints for the hard blocks used within the PHY and clocking structure. A combination of the mapping parameters described above with the hard blockUCF LOC constraints set-up the appropriate routing and usage of the hard blocks. Modification to the MIG 7 Series generated pin-out must be ran through Verify UCF and Update Design to ensure all UCF constraints and rtl parameters are correct. An example of these placements/configuration constraints follow:

Phaser_OUT LOC Constraints:
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y11;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y10;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y9;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y8;

Signal Descriptions

• The User Interface signals and their descriptions can be found under the "Core Architecture" -> "User Interface" and "Interfacing to the Core" -> "User Interface" sections in the7 Series FPGAs Memory Interface Solutions User Guide.
• The Native Interface signals and their descriptions can be found under the "Core Architecture" -> "Native Interface" "Interfacing to the Core" -> "Native Interface" sections in the 7 Series FPGAs Memory Interface Solutions User Guide.
• ThePhysical Interface signals and their descriptions can be found under the "Core Architecture" -> "Memory Controller to PHY Interface" and "Interfacing to the Core" -> "Physical Layer Interface" sections in the 7 Series FPGAs Memory Interface Solutions User Guide.
• See also PHY Only Design Guide (Xilinx Answer 51204)
• For information on the Debug Signals, see (Xilinx Answer 43879)

Linked Answer Records

Master Answer Records

Child Answer Records