AR# 51914


MIG 7 Series DDR3/DDR2 - Generated RTL Parameter, UCF Constraint, and Signal Descriptions


This section of the MIG 7 Series Design Assistant focuses on the signal, UCF constraint,and parameter descriptions of the generated MIG 7 Series DDR3/DDR2 design. Please see the below sections according to your specific questions.
Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Parameter Descriptions
The MIG 7 Series DDR3/DDR2 designs is parameterized by numerous top-level parameters and local-rtl parameters. The local-rtl parameters do not change and should never be edited by a user. Based on the GUI selections and pin-out, MIG properly sets the top-level rtlparameters . The DDR2 and DDR3 Memory Interface Solution > Customizing the Core section of the 7 Series FPGAs Memory Interface Solutions User Guide includes tables which detail each of these top-level rtl parameters. These parameters range from setting up signal widths, simulation options, clock settings, memory controller operation, SDRAM configuration, and mapping of the hard blocks based on the pin-out.

Changes to the pin-out after the MIG 7 Series core has been generated should be ran through the Verify UCF and Update Design feature within the MIG 7 Series tool. The top-level rtl parameters such as BYTE_LANES_B*, DATA_CTL_B*, PHY_*_BITLANES, *_MAP (i.e., ADDR_MAP) are specifically set based on the pin-out MIG 7 Series generates. A combination of thesemapping parameter settings and UCF LOC constraints set-up the appropriate routing and usage of the hard blocks.A change to the pin-out invalidates these settings.

UCF Constraints
The UCF not only includes timing constraints and pin LOCs for the generated design but also LOC and configuration constraints for the hard blocks used within the PHY and clocking structure. A combination of the mapping parameters described above with the hard blockUCF LOC constraints set-up the appropriate routing and usage of the hard blocks. Modification to the MIG 7 Series generated pin-out must be ran through Verify UCF and Update Design to ensure all UCF constraints and rtl parameters are correct. An example of these placements/configuration constraints follow:

Phaser_OUT LOC Constraints:
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y11;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y10;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y9;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y8;

Phaser_IN LOC and Configuration Constraints:
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y8 | DQS_AUTO_RECAL=0 | DQS_FIND_PATTERN="000";

INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y11;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y10;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y9;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y8;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y8;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y2;
INST "*/ddr_phy_4lanes_0.ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y2;

Clocking LOC Constraints:
INST "*/u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y2;
INST "*/u_ddr3_infrastructure/mmcm_i" LOC=MMCME2_ADV_X1Y2;

Signal Descriptions

Linked Answer Records

Master Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
43879 7 Series MIG DDR3/DDR2 - Hardware Debug Guide N/A N/A
51204 MIG 7 Series DDR2/DDR3 - PHY Only Design Guide N/A N/A
AR# 51914
Date 09/20/2012
Status Active
Type Solution Center
People Also Viewed