AR# 51964


LogiCORE IP DisplayPort v3.2 - Clocking Structure for GTP 2-Byte Mode Interface


DisplayPort v3.2 core uses 2-Byte interface in the GTP transceiver. When targeting Spartan-6 FPGA, DisplayPort core uses 1-Byte interface clocking scheme, which is inadequate for DisplayPort implementation.

Spartan-6 FPGA GTP Transceiver User Guide (UG386) -- "GTPCLKOUT Driving a GTP TX in 2-Byte Mode" section provides the correct clocking scheme for 2-Byte interface implementation.



After the DisplayPort v3.2 core is generated, please follow these steps to correct the clocking scheme for use in GTP 2-Byte mode:

1) Find <core_name>_rx_phy.v(hd) module in the <project_directory>/src folder

2) Find the DCM_SP instantiation and un-comment this section. By default, this DCM_SP will be commented out as shown below:

    // Uncomment this code if DCM_SP is to be used instead of BUFIO2
    //     DCM_SP
    //     #(.CLKDV_DIVIDE          (5.000),
    //       .CLKFX_DIVIDE          (20),
    //       .CLKFX_MULTIPLY        (2),
    //       .CLKIN_DIVIDE_BY_2     ("TRUE"),
    //       .CLKIN_PERIOD          (3.704),
    //       .CLKOUT_PHASE_SHIFT    ("NONE"),
    //       .CLK_FEEDBACK          ("1X"),
    //       .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS"),
    //       .PHASE_SHIFT           (0),
    //       .STARTUP_WAIT          ("FALSE"))
    //     rx_div2_inst
    //       // Input clock
    //      (.CLKIN                 (i_clkout0),
    //       .CLKFB                 (i_clkout2_buf),
    //       // Output clocks
    //       .CLK0                  (i_clkout2), // 135 / 81
    //       .CLK90                 (),
    //       .CLK180                (),
    //       .CLK270                (),
    //       .CLK2X                 (i_clkout0_dcm), // 270 / 162
    //       .CLK2X180              (),
    //       .CLKFX                 (),
    //       .CLKFX180              (),
    //       .CLKDV                 (),
    //       // Ports for dynamic phase shift
    //       .PSCLK                 (1'b0),
    //       .PSEN                  (1'b0),
    //       .PSINCDEC              (1'b0),
    //       .PSDONE                (),
    //       // Other control and status signals
    //       .LOCKED                (i_rec_clk_dcm_locked),
    //       .STATUS                (),
    //       .RST                   (~i_pll_lock_detect_tile_0),
    //       // Unused pin- tie low
    //       .DSSEN                 (1'b0));

3) Find the BUFIO2 instantiation and comment this section out. By default, BUFIO2 is used in place of the DCM_SP; an example is shown below:
Note: If using the BUFIO2 please see see (Xilinx Answer 56113)

   // Using BUFIO2 to generate RXUSRCLK2 from GTP rec clock

4) Comment out the following lock signal. Please note that in the <core_name>_rx_phy.v(hd) there will be a few "if generate" statements, you want to edit the following signal from the "spartan6" portion of the code (it should be the first one in this module):
     assign i_rec_clk_dcm_locked = 1'b 1;

5) Edit the following BUFG for clkout_0 signal such that it's now taking an input from i_clkout0_dcm:

    Original BUFG (before):

    BUFG clkout0_bufg_inst
        .O              (i_clkout0_buf),
        .I              (i_clkout0)

    Change it to (after):

    BUFG clkout0_bufg_inst
        .O                (i_clkout0_buf),
        .I                (i_clkout0_dcm)

For a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues, see (Xilinx Answer 33258).

Revision History:
2/6/2013 - Initial Release
2/8/2013 - Edit to the BUFG and Lock signal

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
56113 Design Advisory for Spartan-6 BUFIO2, DIVIDE = 2 Issue N/A N/A
AR# 51964
Date 06/06/2013
Status Archive
Type General Article
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