AR# 5197: Mentor: Possible solution to RAM not simulating correctly in Quicksim II
Mentor: Possible solution to RAM not simulating correctly in Quicksim II
Keywords: RAM, Quicksim, Mentor, simulation
Doing a Functional or Timing simulation of a RAM using Mentor Quicksim II, the RAM comes up in a known state, but none of my write operations appear to be written into the RAM module. Doing a Read on the RAM shows the contents to be the same as what it powered up as.
1) Toggle the //globalsetreset signal at the beginning of the simulation.
2) If it is a timing simulation and the RAM is not coming up in the user defined initial state (INIT property on RAM), make sure that pld_dve is run after running pld_edif2tim. Doing this will add the INIT property as an INSTANCE property for the RAM initialization in the design viewpoint.