2. Support
  3. AR# 5201: 1.5i Map - Virtex mapper fails to pack 2 FMAPs and 2 MUXCY_Ls into one slice.
  4. AR# 52014: Zynq-7000 SoC, Boot IOP - Quad-SPI MIO pin 8 is inadvertently enabled during boot

AR# 52014

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Zynq-7000 SoC, Boot IOP - Quad-SPI MIO pin 8 is inadvertently enabled during boot

Description

The Quad-SPI I/O interface can optionally use MIO pin 8 as a feedback output clock to enable the interface to be clocked at high frequency.
The BootROM inadvertently and unnecessarily enables MIO pin 8 as a toggling output during a Quad-SPI boot sequence.

Solution

The Boot ROM operates the Quad-SPI below the frequency where the feedback output clock is required.

The MIO pin 8 is actively driven with the Quad-SPI clock toggling High and Low. The feedback output clock must be allowed to freely toggle.

 

Impact:
Minor
Work-around:
Board designs should account for MIO pin 8 being an output that toggles during a Quad-SPI boot sequence and take appropriate action.
Configurations Affected:
Systems that use the Quad-SPI boot mode.
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) Zynq-7000 Design Advisory Master Answer Record
AR# 52014
Date 05/25/2018
Status Active
Type Design Advisory
Devices
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