The Quad-SPI I/O interface can optionally use MIO pin 8 as a feedback output clock to enable the interface to be clocked at high frequency.
The BootROM inadvertently and unnecessarily enables MIO pin 8 as a toggling output during a Quad-SPI boot sequence.
Impact:
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Minor
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Work-around:
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Board designs should account for MIO pin 8 being an output that toggles during a Quad-SPI boot sequence and take appropriate action.
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Configurations Affected:
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Systems that use the Quad-SPI boot mode.
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| Device Revision(s) Affected: | Refer to (Xilinx Answer 47916) Zynq-7000 Design Advisory Master Answer Record |
| AR# 52014 | |
|---|---|
| Date | 05/25/2018 |
| Status | Active |
| Type | Design Advisory |
| Devices |
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