When the Quad-SPI I/O interface is used with its internal loopback clock, the value of the qspi.LPBK_DLY_ADJ[4:0] register must be set = 0. This field must be set explicitly by the FSBL or the user application.
|Work-Around:||When it is the boot device.|
|Configurations Affected:||Systems that use the Quad-SPI interface, but do not boot in Quad-SPI mode.|
|Device Revision(s) Affected:||Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record|