How does the PCI v3.0 LogiCORE interface handle single-cycle grants?
Does the assertion of M_ADDR_N always mean that a transaction is starting?
The PCI interface will not assume bus master-ship if the GNT# signal is asserted for only one cycle to the PCI Core.
Due to timing, the PCI Core interface is designed to assert the FRAME# signal after two clocks in which GNT# is asserted. The reason is if GNT# was asserted on clock one and then taken away, a situation might arise wherein the arbiter grants the bus to another master on Clock 2, and the LogiCORE interface and the other master both assert FRAME# on Clock 3. This would cause contention on the bus.
If the core receives a single cycle GNT#, it will still assert M_ADDR_N to the user application; however, this does not mean that the core asserted FRAME# and owns the bus. The user application needs to monitor the M_DATA signal to know whether the core actually owns the bus. M_DATA will assert if GNT# is asserted for two clock cycles or more.
The user application must be designed so that if it is monitoring M_ADDR_N to start a transaction, then if M_DATA does not assert, it has to be able to recover in order to wait for the actual transaction to begin. It is possible to get multiple M_ADDR_N assertions without an M_DATA. Basically, one will occur every time the arbiter gives the device a one cycle only GNT#.
The v3.0 PCI Core will remember that the user has made a request to start a bus transaction. It then continually requests the bus by asserting REQ# until the arbiter gives a two cycle GNT# or better and the data transfer occurs.