AR# 52021


Zynq-7000 SoC, DDR - Read Gate Training value is unreliable in Slice 3


The 4 most significant bits of the Read Gate Training register (used by the PHY trainer) are not valid.

This only applies to Slice 3 of the data and leads to incomplete data being read for the 4 MSBs of this Read Gate training result. 

All four data slices are expected to support 11 bits to present the ratio. The 4 lost bits can be estimated by reading the remaining 7 bits and the 4 MSBs from the other slices.


Impact: Minor. The upper 4 bits of Slice 3 can be estimated, using the results of Slices 0, 1, 2.
Work-around:Estimate the value, see Work-around Details.
Configurations Affected: Systems that use DDR memory and are debugging the Read Gate training results.
Device Revision(s) Affected:Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.


Work-around Details

The work-around computes the best estimate of the missing 4 most-significant bits of the read gate ratio for lane 3.

It uses the read gate ratio of a known good lane as a starting point, and then adds to it the normalized difference in board trace lengths between the known good lane and lane 3.

By comparing the 7 LSB of the estimate to the actual value (which is only 7 bits wide), it is possible to derive the correct value of the 4 MSB, assuming the trace length info is accurate to within about 0.7 inch.

AR# 52021
Date 05/25/2018
Status Active
Type Design Advisory
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