The problem requires the following conditions to occur:
- Some write operations are being handled by the processor and take a long time to complete. The typical situation is when the write operation (STR, STM, etc. ) has missed in the L1 Data Cache.
- No memory barrier (DMB or DSB) is inserted between the write operation and the data cache maintenance operation mentioned in condition 3.
- A data cache maintenance operation is performed, which aborts because of its MMU settings.
- No memory barrier (DMB or DSB) is inserted between the data cache maintenance operation in condition 3 and the ISB in condition 5. Any other kind of code can be executed here, starting with the abort exception handler following the aborted cache maintenance operation.
- An ISB instruction is being executed by the processor.
- No memory barrier (DMB or DSB) is inserted between the ISB in condition 5 and the read or write operation in condition 7.
- A read or write operation is executed.
With the above conditions, an internal "Data Side drain request" signal might remain sticky, causing the ISB to wait for the Data Side to be empty, which never happens because the last read or write operation waits for the ISB to complete.
|Impact:||Minor. The issue can lead to a deadlock; however, it can be prevented through a work-around.|
|Work-around:||A simple work-around for this erratum is to add a DSB at the beginning of the abort exception handler.|
|Configurations Affected: ||Systems that use the CPUs.|
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.|
05/16/2013 - Initial release