For this problem to occur the following conditions must be met:
- Both processors are working in SMP mode (ACTLR.SMP=1)
- One of the processors continuously executes a short loop containing at least one DMB instruction. The short loop must also meet all the following additional conditions:
- The other processor executes a CP15 maintenance operation that is broadcast. This requires that the processor has enabled the broadcasting of CP15 operations (ACTLR.FW=1)
When all these conditions are met, the short loop generates a continuous stream of DMB instructions. This might cause a denial of service by preventing the processor executing the short loop from executing the received broadcast CP15 operation. As a result, the processor that originally executed the broadcast CP15 operation is stalled until the execution of the loop is interrupted.
Note that because the process issuing the CP15 broadcast operation cannot complete operation, it cannot enter any debug-mode, and cannot take any interrupt. If the processor executing the short loop also cannot be interrupted, for example if it has disabled its interrupts, or if no interrupts are routed to this processor, this erratum might cause a system live-lock.
Minor. The erratum might create performance issues, or in the worst case it might cause a system live-lock if the processor executing the DMB is in an infinite loop that cannot be interrupted. However, the occurrence is rare and there is a workaround.
This problem can be worked around by setting bit 4 of the undocumented Diagnostic Control Register to 1. Refer to Work-around Details for more information.
Systems that use the CPUs.
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences Answer Record|
This problem can be worked around by setting bit 4 of the undocumented Diagnostic Control Register to 1. This register is encoded as CP15 c15 0 c0 1. This bit can be written only in the Secure state with the following Read-Modify-Write code sequence:
MRC p15, 0, rt, c15, c0, 1
ORR rt, rt, #0x10
MCR p15, 0, rt, c15, c0, 1
Setting this bit causes the DMB instruction to be decoded and executed like a DSB.
Using this software workaround is not expected to have any impact on the overall performance of the processor on a typical code base.
This problem can also be worked around by doing any of the following: