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AR# 52032

Zynq-7000 AP SoC, APU - Short loop with a DMB instruction might cause a denial of service on another Processor that is attempting to execute a CP15 broadcast operation

Description

A short code loop that includes a DMB instruction might cause a denial of service on another processor that is attempting to execute a CP15 broadcast operation.

Solution

For this problem to occur the following conditions must be met:

- Both processors are working in SMP mode (ACTLR.SMP=1)
- One of the processors continuously executes a short loop containing at least one DMB instruction. The short loop must also meet all the following additional conditions:

  •        No more than 10 instructions other than the DMB are executed between each DMB
  •        No non-conditional Load or Store, or conditional Load or Store which pass the condition code check, are executed between each DMB.

- The other processor executes a CP15 maintenance operation that is broadcast. This requires that the processor has enabled the broadcasting of CP15 operations (ACTLR.FW=1)

When all these conditions are met, the short loop generates a continuous stream of DMB instructions. This might cause a denial of service by preventing the processor executing the short loop from executing the received broadcast CP15 operation. As a result, the processor that originally executed the broadcast CP15 operation is stalled until the execution of the loop is interrupted.

Note that because the process issuing the CP15 broadcast operation cannot complete operation, it cannot enter any debug-mode, and cannot take any interrupt. If the processor executing the short loop also cannot be interrupted, for example if it has disabled its interrupts, or if no interrupts are routed to this processor, this erratum might cause a system live-lock.

 
Impact:
Minor. The erratum might create performance issues, or in the worst case it might cause a system live-lock if the processor executing the DMB is in an infinite loop that cannot be interrupted. However, the occurrence is rare and there is a workaround.
Work-around:
This problem can be worked around by setting bit 4 of the undocumented Diagnostic Control Register to 1. Refer to Work-around Details for more information.
Configurations Affected:
Systems that use the CPUs.
Device Revision(s) Affected: All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences Answer Record


Workaround Details:

This problem can be worked around by setting bit 4 of the undocumented Diagnostic Control Register to 1. This register is encoded as CP15 c15 0 c0 1. This bit can be written only in the Secure state with the following Read-Modify-Write code sequence:

MRC p15, 0, rt, c15, c0, 1
ORR  rt, rt, #0x10
MCR p15, 0, rt, c15, c0, 1


Setting this bit causes the DMB instruction to be decoded and executed like a DSB.

Using this software workaround is not expected to have any impact on the overall performance of the processor on a typical code base.

This problem can also be worked around by doing any of the following:

  •  Inserting a non-conditional Load or Store instruction in the loop between each DMB
  •  Inserting additional instructions in the loop, such as NOPs, to avoid the processor seeing back to back DMB instructions.
  •  Making the processor executing the short loop take regular interrupts.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 52032
Date Created 09/25/2012
Last Updated 05/16/2013
Status Active
Type Design Advisory
Devices
  • XA Zynq-7000
  • Zynq-7000