The LDM PC ^ instructions with base address register write-back might be counted twice in the Performance Monitor event 0x0A, which is counting the number of exception returns.
The associated PMUEVENT signal is also affected by this issue, and might be asserted twice by a single LDM PC ^ with base address register write-back.
Trivial. This issue causes the count of exception returns to be imprecise. The error rate depends on the ratio between exception returns of the form LDM PC ^ with base address register write-back and the total number of exceptions returns. The impact of this issue is typically negligible.
Systems that use the CPUs.
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences Answer Record.|