AR# 52036


Zynq-7000 SoC, APU - CPU performance monitor event 0x0A might count twice the LDM PC ^ instructions


The LDM PC ^ instructions with base address register write-back might be counted twice in the Performance Monitor event 0x0A, which is counting the number of exception returns.

The associated PMUEVENT[11] signal is also affected by this issue, and might be asserted twice by a single LDM PC ^ with base address register write-back.


Trivial. This issue causes the count of exception returns to be imprecise.
The error rate depends on the ratio between exception returns of the form LDM PC ^ with base address register write-back and the total number of exceptions returns.
The impact of this issue is typically negligible.
Configurations Affected:
Systems that use the CPUs.
Device Revision(s) Affected:All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP Silicon Revision Differences Answer Record.


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 52036
Date 05/25/2018
Status Active
Type Design Advisory
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