We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52047

MIG 7 Series Design Assistant - PHY Architecture


The physical interface (PHY) of theMIG 7 SeriesDDR3/DDR2design includesall the hard blocks and soft rtl logic required generate the signal timing and sequencing required to interface to the memory device. This answer record provides details on this block.

Please see the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section of UG586 for detailed information on the PHY.

This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information


Hard Blocks
The MIG 7 Series DDR3/DDR2 design uses a number of hard blocks to generate thesignal timing and sequencing required to send address, control, command, and write data to the memory, and read data from the memory. These include Phaser_IN, Phaser_OUT, IN/OUT_FIFO, PHY_Control, PLL, MMCM, IOLOGIC, and IOBs. These dedicated blocks are structured adjacent to one another with back-to-back interconnects to minimize the clock and datapath routing necessary to build high-performance physical layers. Dedicated clock structures within an I/O bank referred to as byte group clocks help minimize the number of loads driven by the byte group clock drivers. The User Guide goes into sufficient detail to use the MIG 7 Series core with these blocks.

The Phaser_IN, Phaser_OUT, andPHY_Control Blocks are not supported outside of the MIG 7 Series IP cores, and therefore extensive documentation on these blocks is not available nor required. The IN_FIFO and OUT_FIFO are supportedoutside of the MIG 7 Series IP and therefore documented in the 7 Series FPGAs SelectIO Resources User Guide.

Soft RTL Initialization and Calibration

The PHY includes state logic for initializing the SDRAM memory after power-up andcalibration logic to perform timing training of the read and write datapaths to account for system static and dynamic delays.For detailed information, see (Xilinx Answer 51954).

Clock Generation
(Xilinx Answer 40603) Clock Requirements

PHY Only Designs
This section of the MIG 7 Series Design Assistant focusing on the interface between the controller and PHY.
(Xilinx Answer 51204) PHY Only Design Support

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51898 MIG 7 Series DDR3/DDR2 - Design Assistant - PHY Overview N/A N/A

Child Answer Records

AR# 52047
Date 01/23/2013
Status Active
Type Solution Center
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series
  • MIG Virtex-6 and Spartan-6