2. Support
  3. AR# 5204: FPGA Express - Can I run more than one version of FPGA Express on my PC?
  4. AR# 52048: EDK 14.2 Zynq-7000 FSBL - After the axi ports are setup (specifically HP ports), the InitPcap function resets the settings on the HP ports

AR# 52048

EDK 14.2 Zynq-7000 FSBL - After the axi ports are setup (specifically HP ports), the InitPcap function resets the settings on the HP ports

Description

It appears that after the axi ports are set up (specifically HP0 and 1 for 32-bit), the InitPcap() function goes and applies a reset that looks like it wipes out the 32-bit settings on the HP ports.

Solution

In 14.2, the FSBL has an issue where it will reset the registers that control whether the HP ports are configured as 32-bit or 64-bit. A temporary workaround is to modify thefile main.c in the FSBL project by adding the line:

ps7_config(ps7_peripherals_init_data);

before the following lines found near the end of function main():

/* Lock MIO so application cannot mess with control registers */
SlcrLock();
FsblHandoff(HandoffAddress);

The plan is to fix the issue in the 14.3 release.

AR# 52048
Date 09/27/2012
Status Active
Type Known Issues
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