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  3. AR# 52072: Virtex-7 2000T General ES - Known Issues Master Answer Record

AR# 52072

Virtex-7 2000T General ES - Known Issues Master Answer Record

Description

This answer record highlights the important requirements and known issues for the Virtex-7 FPGA General Engineering Sample (GES) program related to software and IP. These items are specifically relevant to designs targeting the Virtex-7 2000T General ES FPGA devices. Additional silicon limitations might exist, so reference the General ES errata that accompanies the devices.

This answer record is updated frequently as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.

Solution

Software Requirements

  • Vivado 2012.3 or higher available on the Xilinx Download Center, is required for use of General ES silicon for Virtex-7 2000T devices

Software Known Issues

  • To be published with the ISE14.x/Vivado Design Suite 2012.x 7 series release
    • (Xilinx Answer 47816) 7 Series - ISE 14.x/Vivado 2012.2 Design Suite Known Issues Related to 7 Series FPGAs
IP Requirements

All 7 series IP cores are listed as Pre-Production in the CORE Generator "Status" field. Support of Pre-Production cores on Initial ES FPGA devices is dependent on Xilinx hardware validation, which is ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues Answer Records below for the most recent information.

IP Known Issues

  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express
    • (Xilinx Answer 47441) Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions
  • 7 Series Integrated Block for PCI Express
    • (Xilinx Answer 40469) 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions
  • MIG 7 Series DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II

Other Important Items

  • (Xilinx Answer 45360) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon

Revision History
02/05/2013 - Updated for 14.x/2012.x
10/22/2012 - Updates
09/27/2012 - Initial release

AR# 52072
Date 02/05/2013
Status Active
Type Known Issues