AR# 52073: Virtex-7 1140T Initial ES and General ES - Known Issues Master Answer Record
Virtex-7 1140T Initial ES and General ES - Known Issues Master Answer Record
This answer record highlights the important requirements and known issues for the Virtex-7 FPGA Initial Engineering Sample (IES) and General Engineering Sample (GES) program related to software and IP. These items are specifically relevant to designs targeting the Virtex-7 1140T IES and GES FPGA devices. Additional silicon limitations might exist, so reference the Initial ES errata that accompanies the devices.
This answer record is updated frequently as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.
Vivado 2012.4 or higher available on the Xilinx Download Center, is required for use of GES silicon for Virtex-7 1140T devices
Vivado 2012.4 or higher available on the Xilinx Download Center, is required for use of IES silicon for Virtex-7 1140T devices
Software Known Issues
To be published with the ISE14.x/VDS 2012.x 7 series release
(Xilinx Answer 47816)7 Series - ISE 14.x/Vivado 2012.2 Design Suite Known Issues Related to 7 Series FPGAs
All 7 series IP cores are listed as Pre-Production in the CORE Generator "Status" field. Support of Pre-Production cores on Initial ES FPGA devices is dependent on Xilinx hardware validation, which is ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues Answer Records below for the most recent information.
IP Known Issues
Virtex-7 FPGA Gen3 Integrated Block for PCI Express
(Xilinx Answer 47441) Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions
7 Series Integrated Block for PCI Express
(Xilinx Answer 40469) 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions
MIG 7 Series DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II