Version Found: MIG 7 Series v1.6
Version Resolved: See (Xilinx Answer 45195)
When the MIG 7 Series FPGAs DDR3 design with the I/O Low Power feature enabled is synthesized using Synplify 2012.09, Synplify inserts an OBUF at the top level, then an IOBUFT_DCIEN lower in the hierarchy.
This creates redundant buffers.
When this netlist is implemented in Vivado, the following error occurs:
When implemented with the ISE tool, NGDBuild removes the redundant OBUF and errors similar to the Vivado flow do not occur:
This error does not occur if Synplify is set to NOT insert I/O buffers.
This error occurs because Synplify is currently missing the timing model for the IOBUFDS_DCIEN primitive.
Because of this, the primitive becomes a blackbox and output buffers get inserted.
To work around this issue until Synplify includes the timing models and prevent OBUF insertion, attributes similar to the following can be applied in the synthesis constraint file: