2. Support
  3. AR# 5213: 1.5i/2.1i: TRCE reports large differences in clock delay (skew) on BUFGLS in XV devices
  4. AR# 52131: MIG 7 Series DDR3/DDR2 - Setting the Traffic Generator to use the PHY_CALIB data pattern on vio_data_mode_value does not work properly.

AR# 52131

MIG 7 Series DDR3/DDR2 - Setting the Traffic Generator to use the PHY_CALIB data pattern on vio_data_mode_value does not work properly.

Description

Version Found: MIG 7 Series v1.7
Version Resolved: See (Xilinx Answer 45195)

Table 1-13: Traffic Generator Signal Descriptions in the 7 Series FPGAs Memory Interface Solutions Guide states that the vio_data_mode_value[3:0] can be set to "0xF: PHY_CALIB pattern."  

This pattern should result in the write calibration data pattern of 0xFF, 00, AA, 55, 55, AA, 99, 66.  

However, the "0xF" setting results in the Address as Data pattern (0x2) mode only generating READ commands at address zero.

Solution

This traffic generator/example design issue is resolved in MIG 7 Series v1.8,  released with ISE 14.4/Vivado 2012.4.

In the meantime, the fixed pattern can be used instead to send this data pattern.
AR# 52131
Date 08/13/2014
Status Active
Type Known Issues
Devices
IP