Version Found: MIG 7 Series v1.7
Version Resolved: See (Xilinx Answer 45195)
If simulating a MIG 7 Series FPGA DDR3 design running at or below 400 MHz, tRFC and tRAS max violations can occur before calibration completes that are similar to the following:
"# sim_tb_top.mem_rnk.mem.gen_mem.*.cmd_task: at time 112279326.0 ps ERROR: tRFC maximum violation during No Op # sim_tb_top.\mem_rnk.gen_mem.*.chk_err: at time 134531257.0 ps
ERROR: tRAS maximum violation during Precharge to bank 0 "
These violations appear before calibration is completed.
The violations occur due to a wait period during the DQS_FOUND stage of calibration and can be safely ignored.
10/16/2012 - Initial release