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  3. AR# 5218: 1.5i, 2.1i COREGEN : What files are required for proper initialization of a Virtex Block RAM in an HDL behavioral simulation? / What is the MIF file?
  4. AR# 52181: MIG 7 Series - Critical warnings are generated when ChipScope cores are used in Vivado

AR# 52181

MIG 7 Series - Critical warnings are generated when ChipScope cores are used in Vivado

Description

Version Found: MIG 7 Series v1.7
Version Resolved: See (Xilinx Answer 45195)

When ChipScope analyzer is added into the MIG 7 Series design, Vivado Design Suite generates the following critical warnings during synthesis:

CRITICAL WARNING: [Synth 8-3321] create_clock attempting to set clock on an unknown port/pin for constraint at line 2 of /proj/ipmig/pboya/mig/mig_7series_v1_7/GUI_Testing/072012/mig_7series_v1_7/example_design/par/proj1.srcs/sources_1/ip/ddr_icon/ddr_icon.constraints/ddr_icon.xdc.

CRITICAL WARNING: [Synth 8-3321] create_generated_clock attempting to set clock on an unknown port/pin for constraint at line 3 of /proj/ipmig/pboya/mig/mig_7series_v1_7/GUI_Testing/072012/mig_7series_v1_7/example_design/par/proj1.srcs/sources_1/ip/ddr_icon/ddr_icon.constraints/ddr_icon.xdc.

Solution

These warnings can be ignored.

Revision History
10/16/2012 - Initial release

AR# 52181
Date 02/18/2013
Status Active
Type Known Issues
Devices
IP