I want to submit my Vivado design project to Xilinx for testing or to reproduce an issue I have seen. However, I would rather not provide the full design as is, due to proprietary concerns.
Is there a way to create a version of my design that has the logic stripped out?
You can use the logic_function_stripped option when writing out either a checkpoint or EDIF file. All logic equations should be turned to XORs and all RAMs will have their contents zero out.
write_edif -logic_function_stripped
write_checkpoint -logic_function_stripped
write_verilog -logic_function_stripped
| AR# 52187 | |
|---|---|
| Date | 10/19/2012 |
| Status | Active |
| Type | General Article |
| Tools |
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