AR# 52198: Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Procedural Assignments
Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Procedural Assignments
This answer record describes SystemVerilog Procedural assignments supported by Vivado Synthesis and also provides coding examples for them. The coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.
Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs covered in each example.
SystemVerilog Procedural Assignments that are supported by Vivado Synthesis
Please refer to Table 1-1 at the end of this AR for the related coding examples.