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  3. AR# 52198: Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Procedural Assignments

AR# 52198

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Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Procedural Assignments

Description

This answer record describes SystemVerilog Procedural assignments supported by Vivado Synthesis and also provides coding examples for them. The coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.
 
Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs covered in each example.

Solution

SystemVerilog Procedural Assignments that are supported by Vivado Synthesis
Please refer to Table 1-1 at the end of this AR for the related coding examples.

1.Conitional if-else statement

example:
          if (expression)
             command1;
         else
            command2;

2.Case Statement
 
example:
            case (expression)
                       value1: statement1;
                       value2: statement2;
                       value3: statement3;
                      default: statement4;
            endcase

3.Loop statement.
 
example:
 
For:
        for (initialization; expression; step)
        statement;

Foreach:

      foreach (a[i]) begin
        $display ("Value of a is %g",i);
      end

do-while:
     do begin
        $display ("Current value of a = %g", a);
        a ++;
      end while  (a < 10);

Coding Examples for Procedural Assigments
Table 1-1
Coding example name Procedural Assignments Used 
 proceduralassignments_example1.zip
  • 1. if-esle
  • 2. case
 proceduralassignments_example2.zip
  • loops 
  • 1. for
  • 2. foreach
  • 3. do-while

Attachments

Associated Attachments

Name File Size File Type
proceduralassignments_example1.zip 1 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51360 Design Assistant for Vivado Synthesis - Help with SystemVerilog Support N/A N/A
AR# 52198
Date 04/03/2013
Status Active
Type Solution Center
Tools
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