Why do I get a Synthesis CRITICALWARNING: [EDIF 20-96] warning when synthesizing the Floating Point Operators with Vivado Synthesis in the 2012.2 tool?
CRITICALWARNING: [EDIF 20-96] Could not resolve non-primitive black box cell 'delay_line__parameterized11_143' defined in file '' instantiated as 'use_DSP48E.appDSP48E.bppDSP48E.need_output_dela
This is a known issue in Vivado Synthesis that is resolved in the Vivado 2012.3 tool.
You can work around this by using XST Synthesis (if you are using the Vivado 2012.2 tool).
For a detailed list of LogiCORE IP Floating Point Operator Release Notes and Known Issues, see (Xilinx Answer 29598).