AR# 52231

MIG 7 Series RLDRAM 3 - Data Mask pins must be placed in the same byte lane as their corresponding data bytes

Description

Version Found: v1.7
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)

When validating a Fixed Pinout in the MIG GUI you may see the following error message:

"Error: All Mask ports should be allocated in single bank."

Solution

Check that you have all Data Mask pins located into a single bank, but also check that each Data Mask pin is placed into the same byte lane as their corresponding data pins. 

For example:

DM[0] should be located in the same byte lane as either DQ[8:0] or DQ[17:9] and DM[1] should be located in the same byte lane as DQ[26:18] or DQ[35:27] for a x18 device.

Additional explanation of this pin-out violation will be provided in a future release.

Revision History
04/03/2013 - Updated to include link to 54025
10/16/2012 - Initial release

AR# 52231
Date 04/16/2014
Status Active
Type Known Issues
Devices
IP