In 2013.3 and 2013.4 versions, this is also supported but you must use the following TCL parameter to enable this feature.
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter supportAsymRam true"
Prior to 2013.3, Vivado Synthesis did not support Asymmetric read/write port width block RAM inference.
Answer Number | Answer Title | Version Found | Version Resolved |
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57854 | 2014.1 Vivado Synthesis - Some patterns of asymmetric BRAM inference are not successful. | N/A | N/A |
AR# 52264 | |
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Date | 04/16/2014 |
Status | Active |
Type | Known Issues |
Tools |