How does the LogiCORE interface handle a target abort?
A target may request an abnormal termination if it detects a fatal error or if it will never be able to complete the request. This is known as a "target abort." A target abort may cause a fatal error for the user application, but the transaction completes successfully, thus preserving normal operation for other agents.
A target abort termination can occur only after the DEVSEL# line has been asserted for at lease one clock cycle. The target signals target abort by deasserting DEVSEL# and asserting STOP# at the same time. Target abort can occur whether or not data is being accessed.
A target abort signals to the present PCI master that it should not repeat the same COMMAND type to the same address (target). It can try a different COMMAND type.
The LogiCORE PCI interface deasserts the FRAME_IO signal after receiving a target abort (asserts STOP_IO). The user application can cause the LogiCORE target interface to signal a target abort and set the "signaled target abort bit (CSR 27)" in the status register by asserting the S_ABORT signal.
A LogiCORE initiator will set the "received target abort bit (CSR 28)" when it detects that an addressed target signaled a target abort.
The "target signaled abort bit (CSR38)" is set after the target signals an abort condition.
| AR# 5227 | |
|---|---|
| Date | 12/15/2012 |
| Status | Active |
| Type | General Article |