AR# 52288


MIG 7 Series DDR2/DDR3 - Byte lane architecture does not support x4 DIMMs


The 7 Series MIG design cannot support x4 DIMMs because of the byte lane architecture.


7 series devices have four byte groups in a bank, and only a single DQS strobe pair available for each byte group. MIG only supports interfaces that span three contiguous vertical banks, and using 16 or 18 DQS strobes (16/18 byte groups) would require more than three contiguous banks. For this reason, MIG does not support x4 DIMMs with 7 series devices.

AR# 52288
Date 10/18/2012
Status Active
Type General Article
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