AR# 52296

LogiCORE IP DisplayPort v3.2 - Is a DCM or PLL required to generate the RXUSRCLK2 for the Spartan-6 FPGA GTP?

Description

Is a PLL or DCM required to generate the RXUSRCLK2 for the Spartan-6 FPGA GTP?

Solution

The example designs in XAPP493 and XAPP593 use the Spartan-6 FPGA PLL/DCM, but is this necessary?

There is reference code that seems to indicate that the PLL or DCM is required, but this code is commented out by default. It is not necessary to use a PLL or DCM to generate the RXUSRCLK2. A BUFIO2 can be used to generate the RXUSRCLK2 input if a PLL or DCM is not available. If using the BUFIO2, please see (Xilinx Answer 56113).

For a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues, see (Xilinx Answer 33258).

Was this Answer Record helpful?

Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
33258	LogiCORE IP DisplayPort - Release Notes and Known Issues	N/A	N/A

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
56113	Design Advisory for Spartan-6 BUFIO2, DIVIDE = 2 Issue	N/A	N/A

AR# 52296
Date	06/06/2013
Status	Archive
Type	General Article
IP	DisplayPort

Page Bookmarked

AR# 52296

LogiCORE IP DisplayPort v3.2 - Is a DCM or PLL required to generate the RXUSRCLK2 for the Spartan-6 FPGA GTP?

Description

Solution

Linked Answer Records

Master Answer Records

Associated Answer Records

Applications

Products

Developer Zone

Support

About Xilinx