When importing functions/tasks in System Verilog Interfaces, ports get connected incorrectly.
Does Vivado Synthesis support import methods (SystemVerilog functions and tasks) from the System Verilog interface?
Starting with 2012.4, Vivado Synthesis does support import methods (SystemVerilog functions and tasks) from the System Verilog interface.
Following is an example of an import method that works:
// function define within an Interface
function example_test (.....);
// Import method
modport test (input a, b, import function example_test( ));
AR# 52300 | |
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Date | 10/25/2013 |
Status | Active |
Type | Known Issues |
Tools |