If a block RAM memory generator HDL code has more than two clocks, the Vivado Synthesis tool generates the following error:
ERROR: [Synth 8-2914] Unsupported RAM template
As an example, where a block RAM memory sub-module HDL code has four clocks; wr0_clk, rd0_clk, wr1_clk and rd1_clk, and the top level module that instantiates this sub-module maps these four clocks to the same clock or two different clocks. The Vivado Synthesis tool will generate the above mentioned error because it considers the actual block RAM memory sub-module that contained the four clocks as having violated the actual Xilinx block RAM primitive supported ports.
The Xilinx block RAM primitive does not support four clocks, and as a result, the Vivado synthesis tool generates the unsupported RAM template error message.
To avoid this problem, a recommended option would be to write block RAM HDL code that adheres to Xilinx block RAM primitive supported ports.