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AR# 52337

Zynq-7000 SoC - Do the MIO pins provide termination?


Do the MIO pins provide input termination or does it need to be provided externally?

The DDR pins of the MIO interface mirror PL HP banks with DCI termination via the VRP/VRN pins, but what about the PS MIO pins?


The general MIO pins mirror HR bank pins, but lack the uncalibrated input termination that the PL version of those pins have.
AR# 52337
Date 05/28/2018
Status Active
Type General Article
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