AR# 52367


MIG 7 Series v1.7 QDRII+ - Per Byte Write Calibration


Starting with MIG 7 Series v1.7,the Write Calibration stage for QDRII+ designs has been enhanced to include per byte write calibration so that each byte lane is calibrated individually.


Write calibration is performed to center the write clocks K/K# into the write data window and without calibrating to each byte individually the a non optimal setting can occur. Here is an example of a scenario that could occur:

You can see from the example that byte lane 2 is not an optimal setting.Per byte calibration should increase data window margin across all byte groups andis already included in the RLDRAM II and RLDRAM 3 Write Calibration stages.
Note: Xilinx recommends upgrading existing 7 Series DDR3 designs to MIG 7 Series v1.7to include thiscalibrationenhancement.
AR# 52367
Date 10/16/2012
Status Active
Type General Article
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