AR# 52409

14.2 EDK, AXI Ethenetlite v1.01.b - Buffers are always instantiated by the IP

Description

The AXI Ethernet lite IP always has buffers instantiated in the netlists. 

When the C_INCLUDE_GLOBAL_BUFFER parameter is set, BUFGs are used and when not, IBUFs are used instead.

Solution

Note: It is recommended that the EDK system be added as a sub-module in the ISE or PlanAhead flow so that the buffers are used appropriately by the tools. 

This answer record describes a work-around for the use-case where the EDK design is instantiated using netlists rather than the recommended flow.

  1. Copy the axi_ethernetlite_v1_01_b IP from the install area ($XILINX_EDK\hw\XilinxProcessorIPLib\pcores\axi_ethernetlite_v1_01_b) to a local repository.
     
  2. Edit the MPD file and remove the BUFFER_TYPE = IBUF tags
     
           Original Text
 
             PORT PHY_tx_clk = "", DIR = I, PERMIT = BASE_USER, BUFFER_TYPE = IBUF, DESC = 'Ethernet Transmit Clock Input', IO_IF = ethernet_0, IO_IS = ETH_TXC
             PORT PHY_rx_clk = "", DIR = I, PERMIT = BASE_USER, BUFFER_TYPE = IBUF, DESC = 'Ethernet Receive Clock Input', IO_IF = ethernet_0, IO_IS = ETH_RXC
 
           New text
 
            PORT PHY_tx_clk = "", DIR = I, PERMIT = BASE_USER, DESC = 'Ethernet Transmit Clock Input', IO_IF = ethernet_0, IO_IS = ETH_TXC
            PORT PHY_rx_clk = "", DIR = I, PERMIT = BASE_USER, DESC = 'Ethernet Receive Clock Input', IO_IF = ethernet_0, IO_IS = ETH_RXC

 3.   Clean and implement the project.
    AR# 52409
    Date 06/08/2020
    Status Active
    Type General Article
    Devices
    Tools
    IP