UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 52447: 7 Series Integrated Block for PCI Express - v1.7 userclk2 incorrectly constrained in XDC file when generating x8Gen2 core

AR# 52447

7 Series Integrated Block for PCI Express - v1.7 userclk2 incorrectly constrained in XDC file when generating x8Gen2 core

Description

Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

When generating the 7 Series Integrated Block for PCI Express v1.7 core, userclk2 is incorrectly constrained to 125 MHz instead of 250 MHz.

Solution

This is a known issue that isscheduled to be fixed in the next release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
10/23/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40469 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 52447
Date 12/17/2012
Status Active
Type Known Issues
IP
  • 7 Series Integrated Block for PCI Express (PCIe)
Page Bookmarked