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  1. Xilinx - All Programmable
  2. Support
  3. AR# 52449: Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 (ISE 14.3 / Vivado 2012.3) - Root Port Configuration Support

AR# 52449

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 (ISE 14.3 / Vivado 2012.3) - Root Port Configuration Support

Description

Version Found: v1.3
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The root port configuration is not supported on the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 core. Users trying to load an old project with root port configuration in CORE Generator will run into an error.

Solution

This is a known issue and is scheduled to be fixed in a future release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
10/23/2012 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47441 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 52449
Date 02/28/2013
Status Active
Type Known Issues
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)