AR# 52452

Description

This Release Notes and Known Issues Answer Record is for the LogiCORE IP Initiator, Target v4.18 for PCI released in ISE Design Suite 14.3 and Vivado 2012.3, and contains the following information:

• General Information
• Supported Devices
• New Features
• Bug Fixes
• Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025):
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.

Solution

General Information

The LogiCORE IP Initiator Target for PCI v4.18 supports Kintex-7, Artix-7, Zynq-7000and Virtex-5 devices. For Spartan-6 architectures, use v4.14. For all other devices, use the v3.167 PCI core. For more information on this core,see (Xilinx Answer 32324).

Supported Devices

• ISE 14.3: All Kintex-7/Artix-7/Zynq-7000/Virtex-5 Devices
• Vivado 2012.3: All Kintex-7/Artix-7 Devices

• ISE 14.3 and Vivado 2012.3 Design Suite support
• Zynq-7000 support with ISE 14.3

• (Xilinx Answer 50880) - LogiCORE IP Initiator, Target v4.17 for PCI - Timing error with slack violation for IRDY_N, on Artix-7 devices
• (Xilinx Answer 45844) - LogiCORE IP Initiator, Target v4.16 for PCI - Implementing Virtex-5 Q device results in ERROR:NgdBuild:604 - logical block 'XPCI_WRAP/XPCI_ADD63' with type

Known Issues

• (Xilinx Answer 50879) - LogiCORE IP Initiator, Target v4.17 for PCI - Simulation fails with " ERROR: Master Abort" in IUS