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AR# 52466

14.2 AXI DDRx - Calibration is not completing in behavioral simulation in ISIM when using VHDL language setting

Description

Calibration is not completing in behavioral simulation when using VHDL language setting. I see Xs on the DQ signals in ISIM.

How can I fix this?

Solution

  1. Open the XPS project, in the System Assembly View right-click on the AXI DDR3 IP and make the IP local.
  2. Navigate to the mcb_raw_wrapper.v file in the project pcores directly, similar to the following:

    pcores\axi_s6_ddrx_v1_06_a\hdl\verilog\mcb_raw_wrapper.v

    Comment out lines 6613 -> 6622:

    // DQS PULLDWON
    //generate
    //if(C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) begin: gen_dqs_pullupdn
    //PULLDOWN dqs_pulldown (.O(mcbx_dram_dqs));
    //end else begin: gen_dqs_pullupdn_ds
    //PULLDOWN dqs_pulldown (.O(mcbx_dram_dqs));
    //PULLUP dqs_n_pullup (.O(mcbx_dram_dqs_n));

    //end
    //endgenerate
  3. Rescan the User repositories in XPS. (Project -> Rescan User Repositories)
  4. Next, Run Behavioral Simulation, and the tools should pick the updated HDL file.
AR# 52466
Date Created 10/18/2012
Last Updated 10/19/2012
Status Active
Type General Article
Tools
  • EDK - 14.1
  • EDK - 14.2
IP
  • AXI Spartan-6 FPGA DDRX Memory Controller