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AR# 52487

7 Series Integrated Block Wrapper for PCI Express v1.7 (ISE 14.3/Vivado 2012.3) - Example Design Reset and Clock Buffer Location for AC701 board

Description

When generating 7Series Integrated Block Wrapper for PCI Express v1.7 core for AC701 Development boards, clock buffer and reset location in the generated XDC/UCF file do not match with the AC701 constraints. To get the example design to work on AC701 Development boards, the clock buffer and reset locations should be modified as follows.

Solution

If you are using an XDC file, please change them as follow in the generated example design's XDC file:

Clock Buffers:

From:
set_property LOC IBUFDS_GTE2_X0Y3 [get_cells refclk_ibuf]
To:
set_property LOC IBUFDS_GTE2_X0Y2 [get_cells refclk_ibuf]

Reset LOC:

From:
set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n]

To:
set_property LOC M20 [get_ports sys_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n]

If you are using a UCF file, please change them as follow in the generated example design's UCF file:

Clock Buffers:

From:
INST "refclk_ibuf" LOC = IBUFDS_GTE2_X0Y3;
To:
INST "refclk_ibuf" LOC = IBUFDS_GTE2_X0Y2;

Reset LOC:

From:
NET "sys_rst_n" IOSTANDARD = LVCMOS18 | PULLUP | NODELAY ;

To:
NET "sys_rst_n" LOC = M20 | IOSTANDARD = LVCMOS33 | PULLUP | NODELAY ;

Revision History:
11/6/2012 - Added UCF Modification
10/18/2012 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51900 Artix-7 FPGA AC701 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 52487
Date Created 11/06/2012
Last Updated 11/30/2012
Status Active
Type Known Issues
Devices
  • Artix-7
Tools
  • ISE Design Suite - 14.3
IP
  • 7 Series Integrated Block for PCI Express (PCIe)