If the ISE design tools generated Place and Route netlist is used, CRC failure is observed in timing simulation, and a TEST PASS and CRC FAIL message is issued by testbench that comes with Aurora 8B10B core.
CRC_PASS_FAIL_N and CRC_VALID signals are used to check valid CRC at the receive side of Aurora 8B10B core. The issue is that the CRC_PASS_FAIL_N signal is asserted before CRC_VALID is asserted.
The following changes need to be made in the simulation/<component name>_tb.v module. Note that #1 delay (in bold) is added into the always blocks.
always @ (posedge crc_pass_fail_n_1)
if(flag_1 == 1)
flag_2 <= 1'b1;
flag_1 <= 1'b0;
always @ (posedge crc_pass_fail_n_2)
if(flag_3 == 1)
flag_4 <= 1'b1;
flag_3 <= 1'b0;
10/30/2012 - Initial release