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  3. AR# 52502: Vivado - A single unconstrained IDELAYCTRL is not automatically replicated as in ISE MAP

AR# 52502

Vivado - A single unconstrained IDELAYCTRL is not automatically replicated as in ISE MAP

Description

In my design, only one unconstrained IDELAYCTRL is instantiated.

The design runs through bitstream generation in ISE without issue.

ISE MAP automatically replicates the IDELAYCTRL and there are three in total in the implementation result.
 
However in Vivado, the replication does not occur.

Since the calibrated IODELAYs span 3 clock regions, write_bitstream issues multiple DRC errors similar to the following:
 

[Drc 23-20] Rule violation (PLIDC-1) IDELAYCTRL DRC Checks - The IODELAY instance 'ADC_UNIT0/adc_interface_dpa_i/IDELAY_CLOCK_RX' has no associated IDelayCtrl. IDELAYCTRL instance is required to calibrate IODELAY instances.

Solution

This can occur when only one IDELAYCTRL is instantiated in a design but the IODELAYs have multiple IODELAY_GROUPs.

Vivado will only replicate the IDELAYCTRL if there is one instantiated and  all IODELAYS are associated with the same IODELAY_GROUP.

Otherwise, you will need to instantiate all IDELAYCTRLs where required.

 

To resolve this issue, ensure that only a single IODELAY_GROUP is used which includes all of the IODELAYs and the instantiated IDELAYCTRL.

for example:

set_property IODELAY_GROUP IODELAY_MIG [get_cells IDELAYCTRL_UNIT]
set_property IODELAY_GROUP IODELAY_MIG [get_cells ADC_UNIT0/adc_interface_dpa_i/IDELAY_CLOCK_RX]      
set_property IODELAY_GROUP IODELAY_MIG [get_cells ADC_UNIT0/adc_interface_dpa_i/IDELAY_RX_DATA_*]  
set_property IODELAY_GROUP IODELAY_MIG [get_cells ADC_UNIT1/adc_interface_dpa_i/IDELAY_CLOCK_RX]      
set_property IODELAY_GROUP IODELAY_MIG [get_cells ADC_UNIT1/adc_interface_dpa_i/IDELAY_RX_DATA_*] 
set_property IODELAY_GROUP IODELAY_MIG [get_cells DDR2_test_unit/u_DDR2_MIG/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_*/ddr_byte_group_io/input_[*].iserdes_dq_.idelaye2]
set_property IODELAY_GROUP IODELAY_MIG [get_cells FB_ADC_UNIT/fbadc_interface_dpa_i/IDELAY_CLOCK_RX]
set_property IODELAY_GROUP IODELAY_MIG [get_cells FB_ADC_UNIT/fbadc_interface_dpa_i/IDELAY_RX_DATA_*]

Note: Although this behavior is different to ISE, it is the expected behavior in Vivado.


AR# 52502
Date 08/28/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2012.2
  • Vivado Design Suite - 2012.3
  • Vivado Design Suite - 2012.4
  • More
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
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