Xilinx Zynq-7000 SoC Solution Center

The Zynq-7000 SoC Solution Center is available to address all questions related to the Zynq-7000 SoC. 

Whether you are starting a new design with Zynq-7000 SoC or troubleshooting a problem, use the Zynq-7000 SoC solution center to guide you to the right information.

QUICK LINKS

UG1046 UltraFast Embedded Design Methodology Guide

Software Developer Solution Center

Boards and Kits Solution Center

Embedded Solutions Forum

Xilinx Open Source Wiki

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Product Page

Design Assistant

Zynq-7000 SoC Design Assistant

The Design Assistant will walk you through the recommended design flow for Zynq-7000 SoC while debugging commonly encountered issues. The Design Assistant will not only provide useful design and troubleshooting information, but also point you to the exact documentation you need to read to help you design efficiently with Zynq-7000 SoC.

Note: This answer record is part of Xilinx Zynq-7000 SoC Solution Center (Xilinx Answer 52512). Xilinx Zynq-7000 SoC Solution Center is available to address all questions related to Zynq-7000 SoC. Whether you are starting a new design with Zynq-7000 SoC or troubleshooting a problem, use the Zynq-7000 SoC Solution Center to guide you to the right information.


Please select the design phase where you have a question or are troubleshooting an issue related to your Zynq-7000 SoC design. 

This will ensure the Zynq-7000 SoC Design Assistant points you to the information you need to continually move forward with your design.

System Design Assistant

(Xilinx Answer 52538) Zynq-7000 SoC Boot and Configuration helps you find all Zynq-7000 SoC answer records related to boot and configuration common questions or known issues
(Xilinx Answer 51779) Zynq-7000 SoC Example Designs and Tech Tips contains useful hints to help with the HW design of your Zynq-7000 Programmable Logic (PL)
(Xilinx Answer 50863) Zynq-7000 SoC Debug keeps track of all the Zynq-7000 SoC answer records related to all the debug solutions available, including debug guides and how to setup third-party debugging tools
(Xilinx Answer 52540) Zynq-7000 SoC FAQs helps you find all Zynq-7000 SoC frequently asked questions

Hardware and IPs Design Assistant

(Xilinx Answer 52539) Zynq-7000 SoC Board Design helps you find all Zynq-7000 SoC answer records related to board design common questions or known issues
(Xilinx Answer 53051) Zynq-7000 SoC - PS DDR Controller helps you find all Zynq-7000 SoC answer records related to the Processing System (PS) DDR Controller (DDRC), including common questions and known issues

Software Design Assistant

(Xilinx Answer 55831) Software Developer Solution Center provides a central location for all known issues relating to Software Development within any of the Xilinx tools (SDK, Vivado Design Suite, etc.)
(Xilinx Answer 52600) Zynq-7000 SoC Standalone Applications Development helps you find all Zynq-7000 SoC answer records related to Standalone common questions or known issues
(Xilinx Answer 52599) Zynq-7000 SoC Operating Systems Development helps you find all Zynq-7000 SoC answer records related to OS' common questions or known issues

Documentation

Zynq-7000 SoC - Documentation

  • Documentation Guide
    • Product Page
    • Product Support Website
    • Document Navigator (DocNav) Database
    • Document Releases
    • Answer Records
    • Forums
    • Internet Searches
  • Device Documents (Xilinx)
  • Device Documents (3rd Party)
  • 7 Series Device Documents Related to Zynq-7000
  • Board Documents
  • Design Tools (Vivado/ISE and SDK)
  • Application Notes

Documentation Guide

Product Page

Be sure to explore the Zynq-7000 SoC Product Page and the other Xilinx Product Pages.


Product Support Website

Find documents on the Xilinx Product Support Website.
Be sure to click the tabs to reveal documentation for Boards and Kits, Programmable Logic IP, Design Tools, Application Notes and White Papers.


Documentation Navigator (DocNav) Database

DocNav is an indexed database of documents for our hardware products, design suites, and other deliverables. DocNav (~100 MBs) can be downloaded from the Xilinx Download webpage. More DocNav information can be found in (Xilinx Answer 50463).

Document Releases

New and updated Zynq-7000 SoC documents are added to our Xilinx Product Support Documentation Website and our DocNav database.
Sign-up for document release notifications. Sign In or create a new account on Xilinx.com and select your notifications.

Answer Records

These articles provide guidance on a range of topics to provide timely and extended knowledge of our products. Find answer records, forums and other documentation using our Search Support Website.

Forums

The Xilinx sponsored forums are listed on our Xilinx User Community Forums Website. Search or Sign In and become a member.

Internet Searches

The internet can also be a very good source of help. Use searches with and without the Xilinx name. Internet searches can be helpful finding resolutions to error and warning messages.

Device Documents (Xilinx)

UG585 Zynq-7000 Technical Reference Manual (TRM) is the comprehensive (1700+ page) user guide that includes architecture, functional descriptions, and detailed descriptions of the control and status registers in Zynq SoC. This user guide is designed for the system architect and register-level programmer. The functionality of the PS side of Zynq SoC is the same for all devices (except for the limitations in the Z-7010 CLG225 device).

All Data Sheets, Errata Sheets, and other User Guides are accessible from the Xilinx Product Support Documentation Website.

DS187, Zynq-7000 SoC (7010 and 7020): AC and DC Switching Characteristics Data Sheet
DS191, Zynq-7000 SoC (7030, 7045, and 7100): AC and DC Switching Characteristics Data Sheet
UG865, Zynq-7000 SoC Packaging and Pinout Specifications
UG821, Zynq-7000 SoC Software Developers Guide
UG933, Zynq-7000 SoC PCB Design and Pin Planning Guide
(Xilinx Answer 47916) Lists the Errata Sheets and Related Answer Records

The Zynq-7000 TRM also includes an appendix of documentation links.


Device Documents (3rd Party)

IP suppliers for PS resources are listed in (Xilinx Answer 47921). Also visit the ARM Infocenter Website.

UG585 Zynq-7000 TRM includes a list of third party IP. Xilinx is only able to provide ARM third party documentation links.


7 Series Device Documents Related to Zynq-7000

The programmable logic in Zynq SoC is very similar to the 7 Series Artix and Kintex FPGAs. The PL resources are described in the Programmable Logic Description chapter of the UG585 Zynq-7000 TRM. The Zynq-7000 TRM Appendix includes a list of Xilinx 7 Series documents.


Board Documents

Visit AR43746 - Xilinx Boards and Kits Solution Center - Documentation for a full list of Xilinx Board Kits and their associated documents.

Visit ZedBoard.org, a community-based website featuring Avnet's development boards based on the Zynq-7000 7z020 and 7z010 devices.


Revision History
August 2013: Revamped.


Design Advisories

Design Advisory Master Answer Record for Zynq-7000 SoC Devices

The Zynq-7000 devices are documented in the Zynq data sheet, technical reference manual and other documents.

Important design advisories and other considerations that transcend these documents are listed here.

The source point for technical content begins in the Xilinx Zynq-7000 SoC Solution Center (Xilinx Answer 52512).


Design Advisories Alerted on September 17th, 2018
(Xilinx Answer 71437)Design Advisory for Zynq-7000: 2018.2 (and earlier) U-Boot does not authenticate the partition header.  [SECURITY]
(Xilinx Answer 71436)Design Advisory for Zynq-7000: 2018.2 (and earlier) U-Boot does not use the PPK verified by BootROM and stored in OCM when loading partitions.[SECURITY]

Design Advisories Alerted on August 6th, 2018

(Xilinx Answer 71225)Design Advisory for Zynq-7000: FSBL authenticates the boot image in external DDR[SECURITY]
(Xilinx Answer 71292)Design Advisory for Zynq-7000: FSBL performs the security operations on the partitions based on the content of the partition headers.[SECURITY]

Design Advisories Alerted on April 9th, 2018

(Xilinx Answer 70537)Design Advisory for Zynq-7000 SoC RSVDGND Pin and PL STARTUPE2 Primitive Requirements in all ISE versions and Vivado 2017.2 and earlier versions

 

Design Advisories Alerted on November 1st, 2016

(Xilinx Answer 68006)Design Advisory for Xilinx Design Tools (Vivado, SDAccel, SDSoC) 2016.1 and 2016.2 write_bitstream - Multi-threading might cause configuration memory cells to be set incorrectly

 

Design Advisory Alerted on August 8, 2016

(Xilinx Answer 66871)7 Series FPGA and Zynq-7000 SoC HR I/O Transition during power-on

Design Advisory Alerted on November 2, 2015

(Xilinx Answer 65688)Design Advisory for Zynq-7000 PS DDR: High temperature derating may be insufficient for LPDDR2 DRAM

Design Advisory Alerted on October 19, 2015

(Xilinx Answer 65145)Design Advisory for Zynq-7000 PS DDR- DDR3 CKE deassertion time is too short

Design Advisory Alerted on September 14, 2015


(Xilinx Answer 65240)Design Advisory for Zynq-7000 SoC: Power-On/-Off Sequence Requirements for PS eFUSE Integrity 

Design Advisory Alerted on February 23, 2015


(Xilinx Answer 63149)Design Advisory for Zynq-7000 SoC: Secure Lockdown triggered by PS_POR_B reset sequence

 

 

Design Advisory Alerted on June 23, 2014


(Xilinx Answer 60848)Design Advisory for Zynq-7000 SoC: Static Memory Controller, Parallel (SRAM/NOR) Interface 64MB configuration issues

 

Design Advisory Alerted on June 2, 2014


(Xilinx Answer 60454)Design Advisory Zynq-7000 PS DDR Controller - DDR IO's are not properly configured in ISE/EDK and Vivado 2013.3 and earlier

 

Design Advisory Alerted on April 28, 2014


(Xilinx Answer 59999)Design Advisory for Zynq-7000 SoC, eMMC - JEDEC standard 4.41 requires input hold tie of 3 ns.

Design Advisories Alerted on December 9, 2013


(Xilinx Answer 57930)Design Advisory for Zynq-7000 SoC - Boundary Scan test fails when VMODE is set to 1.8V
(Xilinx Answer 58694)Design Advisory for Zynq-7000 SoC - Updated UG933 may require additional decoupling capacitors in some cases

 

Design Advisory Alerted on October 14, 2013


(Xilinx Answer 57744)Design Advisory for Zynq-7000 SoC - Zynq and QSPI reset requirements when using larger than 16MB flash

 

Design Advisory Alerted on September 16, 2013


(Xilinx Answer 57193)Design Advisory for the Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed

 

Design Advisory Alerted on June 24, 2013


(Xilinx Answer 56195)Design Advisory for Zynq-7000 SoC - Why does a design that worked with ES silicon now fail to boot with production silicon?

 

Design Advisories Alerted on February 18, 2013


(Xilinx Answer 47916)Answer Records related to errata items: Zynq-7000 SoC Devices - Silicon Revision Differences
(Xilinx Answer 53450)Design Advisory for Zynq-7000 SoC, USB - ULPI interface requires input hold time of 1 ns
(Xilinx Answer 54190)Design Advisory for Zynq-7000 SoC, APU - L2 cache Operation Requires Programming of the slcr.L2C_RAM Register
(Xilinx Answer 54195)Design Advisory for Zynq-7000 VCCPLL Sensitivity