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AR# 52541

MIG v1.7 DDR3/DDR2 - Increase in simulation time between v1.6 and v1.7

Description

During calibration, the DQSFOUND stage aligns the different DQS groups to the same PHY_Clk and finds the optimal read data offset position with respect to the read command. The DQSFOUND calibration logic issues sets of four back-to-back reads with gaps in between. Starting with MIG 7 Series v1.7, additional sets of four back-to-back read cycles were added. Because of this, simulation time will increase. As an example, a MIG v1.6 simulation that took 5 minutes to complete calibration will take 10 minutes to complete with MIG 1.7.

This answer record details a work-around to reduce simulation time with the MIG v1.7 design. The work-around noted will be included by default in MIG 7 Series v1.8.

Solution

To reduce the simulation time, complete the following steps:

  1. Open the user_design/phy/mig_7series_*_ddr_phy_dqs_found_cal.v or the user_design/phy/mig_7series_*_ddr_phy_dqs_found_cal_hr.v for designs in HR I/O.
  2. Add a local parameter to reduce the number of back-to-back reads issued during DQSFOUND Calibration:
    localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
  3. Modify the always block starting on line 377 to use the fast simulation option.
    Modify from:
    always @(posedge clk) begin
    if (rst || (detect_rd_cnt == 'd0))
    detect_rd_cnt <= #TCQ 'd7;
    else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
    detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
    end

    To:
    always @(posedge clk) begin
    if (rst || (detect_rd_cnt == 'd0))
    detect_rd_cnt <= #TCQ NUM_READS;
    else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
    detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
    end
  4. Run the simulation again.
AR# 52541
Date Created 10/22/2012
Last Updated 10/24/2012
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series