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  3. AR# 5255: SIMPRIM, Timing Simulation - What are "$setup" and "$hold" violations, and how do I fix them? (VHDL, Verilog)
  4. AR# 52558: 14.2 Route - "ERROR:Route:471 - This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be routed."

AR# 52558

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14.2 Route - "ERROR:Route:471 - This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be routed."

Description

An unrouteable issue has been seen on a Virtex-6 device that involves an IDDR_2CLK primitive with both S and R ports used which leads to an unsupported and unroutable configuration using the REV pin.

The REV pin exists in the device model but has no routing resources and so the failure mode is an unroutable design message with no details:

ERROR:Route:471 -
   This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be
   routed:
Unrouteable Net:GLOBAL_LOGIC1

Solution

Instantiating the IDDR with the correct connectivity will resolve the issue.

Also, a LIT DRC check will be added in ISE 14.4 to inform of the incorrect connectivity.
AR# 52558
Date 07/31/2014
Status Active
Type General Article
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