The following errors are returned by Vivado Synthesis. How can I resolve this issue?
Error: [Synth 8-2442] non-net port I_CLK cannot be of mode input ["*/demo.v":40]
Error: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
These errors occur because the default net type is changed by the `default_nettype directive.
To resolve the error, use either of the following solutions:
1) Set the default net type to wire by deleting the `default_nettype directive or redefining it with the directive "`default_nettype wire".
Note: The files affected by the `default_nettype directive are related to the compile order. This will affect all files compiled after the directive is taken until another directive supersedes it.
2) Explicitly declare the input port as a wire.
For example:
`default_nettype none
module my_module
(
input wire clk,
input wire reset,
input wire data_in,
output reg data_out
);
| AR# 52648 | |
|---|---|
| Date | 10/10/2016 |
| Status | Active |
| Type | General Article |
| Tools | |