Description

The 7 Series Integrated Block for PCI Express core does not link up successfully on an Intel Z77 (Ivy Bridge) platform.

This affects the out-of-box experience for customers wanting to use the Zynq-7000 PCIe Targeted Reference Design (v1.0) running with ISE 14.3 design tools on the ZC706 Evaluation Kit.

Solution

For ISE 14.3 design tools, to resolve this issue, perform the following steps:

1. Unzip the reference design ZIP file.
2. Browse to z7_pcie_trd_v1_0/prog_qspi.
3. Copy the bin file (zc706_pcie_trd.bin), attached at the end of this answer record, into the prog_qspi folder. The bin file addresses Intel errata BV56 (PCI Express* Gen3 Receiver Return Loss May Exceed Specifications). 
   To work around this issue, TX_RXDETECT_REF is set to 3'b010 in gt_wrapper.v.  By default, this parameter is set to: 3'b100.  The Intel errata can be found at:
   http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdf
   
4. Follow the instructions in the Zynq-7000 All Programmable SoC ZC706 Evaluation Kit Getting Started Guide to setup and run the TRD with the following exception:
   In the TRD demonstration section connect an external 12V wall power supply to the ZC706 board instead of the ATX power supply.  The FPGA configuration time on the ZC706 board is large and does not meet the PCIe specification.  By the time the FPGA configures, PCIe enumeration on the host system is complete.

Using an external power supply is an interim solution. A Tandem configuration bin file which will meet the PCIe specification without the need for an external power supply should be available in the next release of the TRD.

In 14.4, the ZC706 PCIe Base Targeted Reference design bin file, zc706_pcie_trd.bin, was updated accordingly with 14.4 recommendations (TX_RXDETECT_REF set to 3'b011).  The changes in this Answer Record are no longer required from 14.4 and beyond.

Attachments

Associated Attachments

Linked Answer Records

Master Answer Records