Synthesis and implementation of my design run successfully. However, when I try to generate the programming file (.bit), the following error occurs:
ERROR:Bitgen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported. Please see the informational messages in the NGDBUILD report file for this design, <designname>.bld, to determine which core causes this error.
When I check the NGDBUILD report, I find the following INFO message:
WARNING:NgdBuild:1342 - No bitstream will be generated for this design because bitstream generation is prohibited for core <v_tc>. Please regenerate this core with its full IP license installed.
The BitGen error is a general message which is issued whenever an IP in the project does not have a license required for bitstream generation.
For more information on when IP licenses are checked, see (Xilinx Answer 44030).
Because Licensing information is embedded in the IP core at the time of generation, the IP core will need to be regenerated if the proper license was not available when the IP core was first generated; see (Xilinx Answer 30517).
A specific case where this issue has come up multiple times is for Zynq board users with a targeted design. The targeted design project that comes with some Zynq board kits has an XPS file in it, which contains the v_tc core and v_cfa cores. The v_tc and v_cfa IP require a full or evaluation license. Many users implementing this example design get the Zynq device locked license only and run into the above error in bitstream generation. Evaluation licenses for the v_tc and v_cfa IP are available for generation at www.xilinx.com\getlicense.
After generating the v_cfa Evaluation License from the entitlement website and again regenerating the XPS file, the design ran successfully through BitGen.
To regenerate the cores, which exist in the XPS file, follow these steps.